In designing large scale integration (LSI) circuits or very large scale integration (VLSI) circuits, one important step is to incorporate testing circuits for the designs. The principle is to proceed testing methods concurrently with the architectural considerations of the designs as opposed to be left until fabricated chip or components of the chip have been made. This manufacturing test principle has been well recognized by the LSI and VLSI design industry.
The testing of large scale integration (LSI) packages, very large scale integration (VLSI) packages, and application-specific integrated circuits (ASIC) has become increasingly important as these components and circuits continue to increase in gate densities. With every successive generation having a greater number of gates to test, identifying critical paths in an IC chip becomes more and more important. A critical path (or called critical timing path) is a logical path that runs slower than predicted or slower than any other logical paths in the system. Typically it is very complicated to actually figure out a number of critical timing paths, for example the top ten critical timing paths on a silicon chip. There are timing tools that are used to predict a given set of logical paths. However, when the chip is tested in hardware, typically the logical paths predicted by timing tools can change. Accordingly, it is often desirable to have as many tools as possible to ease the finding of critical paths when there is hardware in hand.
A collection of test techniques have evolved over the history of the IC chip designs. One test technique is the Scan-based test technique which includes a popular approach called Level Sensitive Scan Design or the LSSD approach. Certain desired logic test patterns are serially inputted and shifted to the appropriate latch locations when the functional logic unit is operated in a "shift mode" (i.e., by withholding system clock excitations and turning on shift scan control signals to the functional logic unit). When this is done, the latch states will provide the desired stimuli for the testing of the related logic nets. Next, the test patterns are propagated through the nets by executing one or more steps of the "function mode" operation (i.e., by exercising one or more system clock excitations). The response patterns of the logic networks to the applied stimuli is captured by the system latches, in a known manner depending on certain details of hardware design, often replacing the original inputted test patterns. Then, the system reverts to the shift-mode operation, outputting the response patterns for examination and comparison with expected patterns which should be present if the circuitry has operated properly. The scan-based test is typically employed to test the component chips of the package as well as the package. The technique logically partitions the dense scan logic into portions which are bounded on the inputs and outputs by Shift Register Latches (SRLs) and package pins wherever system logic dictates. Tests are then generated individually for each partition. Other approaches of the scan-based test techniques have also been developed, such as serial scan, partial serial scan, parallel scan techniques, etc.
Another collection of test techniques evolved over the history of the chip designs is built-in self-test techniques. As the names have suggested, built-in self-test techniques rely on augmenting circuits to allow them to perform operations on themselves that prove correct or incorrect operations. One method of incorporating a built-in self-test module is to use signature analysis or cyclic-redundancy checking. This involves the use of a pseudo-random sequence generator (PRSG) to generate the input signals for a section of combined circuitry and then using a signature analyzer to observe the output signals. Signature analysis can be merged with the scan technique to create a structure known as Built-In Logic Block Observation (BILBO). Other built-in self-test methods including memory self-test and iterative logic array test techniques, etc.
Generally, a built-in self-test apparatus is provided for testing the overall functional operation of an IC chip which has microprocessor, RAM, ROM, PROM, address latch, I/O, functional logic units, buses, and other electronic circuits in the system.
U.S. Pat. No. 5,663,966 issued to Day et al., issued date Sep. 2, 1997, assigned to the common assignee of the present invention, International Business Machines Corporation, describes the scan-based testing in details, which is incorporated by reference.
U.S. Pat. No. 5,018,144 issued to Corr et al., issued date May 21, 1991, assigned to the common assignee of the present invention, International Business Machines Corporation, describes a scan test system providing an inexpensive transition fault test by changing the sequence of application of A/C and B clocks. Corr et al. discloses that in each machine test cycle, the B clock is triggered first, and the A/C clock is triggered second. Since the periodicity of the clocks is not changed for a particular cycle, less sophisticated scan test equipment can provide both transition fault and stuck fault testing.
A built-in self-test system described in U.S. Pat. No. 4,377,757 issued to Konemann et al., issued date Mar. 22, 1983, describes logic modules for integrated digital circuits and means for incorporating the logic modules for test pattern generation and for parallel test data monitoring to individually test circuit portions or modules of complex circuits.
U.S. Pat. No. 5,612,963, issued to Koenemann, et al., assigned to the common assignee of the present invention, International Business Machines Corporation, describes a hybrid pattern self-testing of integrated circuits employed in an on-chip fashion to provide desired test signals to circuits on the chip by means of the weighted random pattern method.
One existing built-in self-test system is used to test a system having a multiplier portion of the FPU (Floating Point Unit). The multiplier portion of the FPU can be designed as a dual rail to increase the speed of the logic. During a test operation, a testing system is usually not able to recognize the dual rail to guarantee that both sides of the rail always complementary during the random pattern generation of the test data bits. Control latches have been added to select one rail, both rails, or no rails during the test. However, this defeats the speed bonus of the dual rail design. Accordingly, the multiplier is being skipped or removed during the testing operation. The skipping or removing or deselecting of the multiplier during a testing operation is in fact predefined based on the system's desire.
Another existing built-in self-test system is used to a system having potentially problematic logic, such as Array Built-In Self-Test (ABIST) logic. In this case, a similar skipping or removing or deselecting of the problematic logic during the test is currently used. Again, the skipping or removing or deselecting of the particular problematic area during a testing operation is predefined based on the system's desire.
Even with the above and other existing testing techniques, it is still very difficult and complicated to actually select/deselect any combination of functional units of system logic to figure out what a number of the top critical timing paths on a chip are. One of the main concerns is that even though the timing tools predict a given set of critical timing paths, when the chip is tested in hardware, these paths usually change. Therefore, there is a need for as many test tools as possible to ease the finding of a number of critical timing paths.
The present invention provides a system and method for finding a number of critical timing paths in a chip by running a Logic Built-In Self-Test (LBIST) on a given or selected functional piece of logic (or referred to functional unit) in a chip. The present invention provides a solution to the above and other problems and offers other advantages over the prior art.